Event DevRel Lead

. !Tenstorrent Logo Current openings at Tenstorrent Search Department Select... Office Select... 82 jobs Tensix | Job | | --- | | Performance Architect, AI HW\<br>\<br>Toronto, Ontario, Canada | | Power Architect\<br>\<br>Toronto, Ontario, Canada | | Risc-V Architect\<br>\<br>Toronto, Ontario, Canada | | Senior Design Verification Engineer, AI HW\<br>\<br>Toronto, Ontario, Canada | | Silicon Lead, Automotive/Robotics\<br>\<br>Toronto, Ontario, Canada | Architecture | Job | | --- | | Fabric SOC Architect\<br>\<br>United States | | High-Performance Computing Architect\<br>\<br>United States | | Memory Architect\<br>\<br>North America | | Power Architect, AI Data Center Chiplets\<br>\<br>United States | | Project Administrator\<br>\<br>Tokyo, Japan | | Senior DFT Engineer, Architecture\<br>\<br>Japan | | Verification Engineer \<br>\<br>Japan | Automotive Architecture | Job | | --- | | Automotive and Robotics SOC Architect \<br>\<br>United States | CPU | Job | | --- | | RISC-V CPU Microarchitecture / RTL \<br>\<br>United States | Design Verification | Job | | --- | | Formal Verification Lead\<br>\<br>United States | Performance Model | Job | | --- | | CPU Architect, Load-Store\<br>\<br>United States | Physical Engineering | Job | | --- | | Staff Technical Program Manager, Physical Design\<br>\<br>Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States | | Technical Program Manager, RISC-V IP\<br>\<br>United States | Mixed Signal Design | Job | | --- | | Silicon Validation EngineerNew\<br>\<br>Santa Clara, California, United States | Packaging | Job | | --- | | Package Design EngineerNew\<br>\<br>Toronto, Ontario, Canada; 新北市, New Taipei City, Taiwan | Physical Design | Job | | --- | | CPU/AI/SOC Physical Design Lead\<br>\<br>Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States | | Physical Design Engineer - Power Grid/EMIR\<br>\<br>Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States; United States | | Physical Design Engineer - STA\<br>\<br>Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States; United States | | Physical Design Flow EngineerNew\<br>\<br>Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States | | Senior Physical Design Engineer\<br>\<br>Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States | | SoC Physical Design Verification Engineer\<br>\<br>Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States | | SoC Top-Level Physical Design Engineer\<br>\<br>Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States | | Staff Physical Design Engineer – EMIR\<br>\<br>Austin, Texas, United States; Santa Clara, California, United States | RISC V | Job | | --- | | Director, RISC-V Software Ecosystem\<br>\<br>United States | | Sr. Staff Engineer, Automotive System Software\<br>\<br>United States | | Sr. Staff Engineer, Emulation Validation Lead\<br>\<br>Austin, Texas, United States | | Sr Staff Software Engineer, Toolchain/Compiler \<br>\<br>United States | | Staff Engineer, Platform Security Systems Software\<br>\<br>United States | DevInfra and ML | Job | | --- | | Sr. Staff Engineer, DevOps - Automation and Software Tooling\<br>\<br>United States | | Sr. Staff Engineer, Hardware Infrastructure Lead\<br>\<br>Austin, Texas, United States; Santa Clara, California, United States | | Staff Engineer, HPC Infrastructure\<br>\<br>Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada | | Staff Engineer, HPC Systems Software\<br>\<br>Austin, Texas, United States; Santa Clara, California, United States; United States | Platform Software | Job | | --- | | Staff Engineer, Systems Software\<br>\<br>Australia; United States | Silicon | Job | | --- | | Staff Design for Test Engineer\<br>\<br>Austin, Texas, United States; Santa Clara, California, United States | | Staff, Design for Test Engineer (DFT)\<br>\<br>Bengaluru, Karnataka, India | DFT and Test | Job | | --- | | Staff Design for Test STA Engineer\<br>\<br>Santa Clara, California, United States | Engineerin